Verilog.txt
Version 0.6 Based on IEEE Standard Verilog Hardware Description Language
            IEEE Std. 1364-2001 later 1364-2005

Clause 5.1 page 64
"Although the Verilog HDL is used for more than just simulation,
 the semantics of the language are defined for simulation,
 and everything else is abstracted from this base definition."

CAUTION: This information is based on the IEEE standard.
Most constructs have been tested on some Verilog compiler, but
no compiler, yet, handles the complete standard language.
You may not be able to use some features on a specific compiler.

Syntactical Entities
  Verilog is case sensitive
  // makes rest of line a comment

  identifiers: start with a letter or underscore "_"
               contain letters, numbers, "_" and dollar sign "$"
               may contain any non-whitespace escaped character \<character>

  operators and special characters:
    +    addition
    -    subtraction
    *    multiplication
    /    division
    **   exponentiation
    %    modulus
    >    greater than relation         // relations are 0 if false
    <    less than relation            // 1 if true and possibly x
    >=   grater than or equal relation
    <=   less than or equal relation
    ==   logical equality relation 
    !=   logical inequality relation
    ===  case equality   // x must match x, z must match z
    !==  case not equal  // comparison is made bit-wise
    &&   logical and
    ||   logical or
    !    logical negation
    &    bit-wise and (also unary reduction and)
    ~&   unary reduction nand
    |    bit-wise or (also unary reduction or, event or)
    ~|   reduction nor
    ^    bit-wise exclusive or (unary reduction xor)
    ~^   bit-wise equivalence (^~) (also unary reduction xnor)
    ~    bit-wise complement 
    >>   bit-wise logical right shift
    <<   bit-wise logical left shift
    >>>  bit-wise arithmetic right shift
    <<<  bit-wise arithmetic left shift
    ? :  condition ? value-if-true : value-if-false
    ?    compare equal on this bit
    *    compare equal on group of bits
    =    substitution
    <=   non blocking substitution
    :    separator
    ,    separator
    .    selector  .parameter(actual)  module_name.local_name  
    ;    statement terminator

    ( )  grouping parenthesis, module instantiation, function and task call
    [ ]  subscript, range as in [31:0]
    { }  concatenation
    " "  pair of quotes around strings

    @    event control
    `    compiler directive
    $    system task and functions

    /*   start comment
    */   end comment
    //   start comment to end of line
    (*   start non simulation attribute
    *)   end non simulation attribute

    '    constant  width'radix value  base is b B d D h H o O 
    %    format indication b B c C d D e E f F g G h H l L m M o O
                           s S t T u U v V z Z  %10.5E  %0d
    \    escape sequences, quoted characters in strings \n \t \\ \" \ddd %%

  numbers:
     3  123456 
     width'radix value
             width is integer, automatic extension to 16 bits
             radix is d or D for integer (optional)
                      h or H for hexadecimal
                      o or O for octal
                      b or B for bit

                         'h ff  is 00ff hex // default 16 bit
                       16'h ff  is 00ff hex
                        1'b 1   or just 1
                        1'b 0   or just 0
                        1'b x   needed for x unknown
                        1'b z   needed for z high impedance
                        8'B0110_1100  binary 01101100 8-bits

     real  1.0  0.1  123e-5  123.0E-5  per IEEE 754-1985

     "a string"  constant string, no extra characters, no terminator

Keywords (Reserved Words)

  always            starts an  always begin ... end  sequential code block
  and               gate primitive, and
  assign            parallel continuous assignment
  automatic         a function attribute, basically reentrant and recursive
  begin             starts a block that ends with  end (no semicolon)
  buf               gate primitive, buffer
  bufif0            gate primitive, buffer if control==0
  bufif1            gate primitive, buffer if control==1
  case              starts a case statement
  casex             starts a case statement where x matches
  casez             starts a case statement where z matches
  cell              library, cell indentifier, in configuration
  cmos              switch primitive, cmos
  config            starts a configuration
  deassign          stops the corresponding  assign  from accepting new values
  default           optional last clause in a case statement
  defparam          used to over-ride parameter values
  design            top level module, in configuration
  disable           a task or block
  edge              edge control specifier
  else              execute if no previous clause was true
  end               end of a block, paired with a begin
  endcase           end of a case statement
  endconfig         end of a configuration
  endfunction       end of a function definition
  endgenerate       end of a generate
  endmodule         end of a module definition
  endprimitive      end of a primitive definition
  endspecify        end of a specify
  endtable          end of a table definition
  endtask           end of a task definition
  event             data type
  for               starts a for statement
  force             starts net or variable assignment
  forever           starts a loop statement
  fork              begin parallel execution of sequential code
  function          starts a function definition
  generate          starts a generate block
  genvar            defines a generate variable
  highz0            drive strength 0
  highz1            drive strength 0
  if                starts an  if  statement, if(condition) ...
  ifnone            state dependent path declaration
  incdir            file path for library
  include           include file specification
  initial           starts an initial begin ... end sequential block
  inout             declares a port name to be both input and output
  input             declares a port name to be input
  instance          specify instance name, in configuration
  integer           variable data type, 32 bit integer
  join              end of a parallel fork
  large             charge strength, 4, of trireg
  liblist           library search order for modules, in configuration
  library           location of modules, libraries and files
  localparam        starts a local parameter statement, not over-ridden
  macromodule       same as module with possibly extra meanings  
  medium            charge strength, 2, of trireg
  module            begin a module definition, also called a cell or component
  nand              gate primitive, nand
  negedge           event expression, negative edge
  nmos              switch primitive, nmos
  nor               gate primitive, nor
  noshowcancelled   no report trailing edge precedes leading edge, in specify
  not               gate primitive, not
  notif0            gate primitive, not if control==0
  notif1            gate primitive, not if control==1
  or                gate primitive, or
  output            declares a port name to be an output
  parameter         starts a parameter statement
  pmos              switch primitive, pmos
  posedge           event expression, positive edge
  primitive         starts the definition of a primitive module
  pull0             drive strength 5
  pull1             drive strength 5
  pulldown          gate primitive
  pullup            gate primitive
  pulsestyle_onevent glitch detection, in specify
  pulsestyle_ondetect glitch detection, immediate change to x, in specify
  remos             switch primitive, remos
  real              variable data type, implementation defined floating point
  realtime          variable data type, floating point time
  reg               variable data type, starts a declaration of name(s)
  release           release a forced net or variable assignment
  repeat            starts a loop statement
  rnmos             switch primitive, rnmos
  rpmos             switch primitive, rpmos
  rtran             bidirectional switch primitive, rtran
  rtranif0          bidirectional switch primitive, rtranif0
  rtranif1          bidirectional switch primitive, rtranif1
  scalared          property of a vector type
  showcancelled     report trailing edge preceeds leading edge, in specify
  signed            type modifier, reg signed
  small             charge strength, 1,  of trireg
  specify           starts a specify block
  specparam         starts a parameter statement for timing delays
  strong0           drive strength 6
  strong1           drive strength 6
  supply0           net data type, and drive strength 7
  supply1           net data type, and drive strength 7
  table             start a table definition in a primitive
  task              starts a task definition
  time              variable data type, 64 bit integer
  tran              bidirectional switch primitive, tran
  tranif0           bidirectional switch primitive, tranif0
  tranif1           bidirectional switch primitive, tranif1
  tri               net data type
  tri0              net data type, connected to VSS
  tri1              net data type, connected to VDD
  triand            net data type, tri state wired and
  trior             net data type, tri state wired or
  trireg            register data type associates capacitance to the net
  unsigned          type modifier, unsigned
  use               library, cell identifier, in configuration
  vectored          property of a vector type
  wait              starts a wait statement
  wand              net data type, wired and
  weak0             drive strength 3
  weak1             drive strength 3
  while             starts a sequential looping statement, while(condition) 
  wire              net data type, a basic wire connection
  wor               net data type, wired or
  xnor              gate primitive, xnor not of exclusive or
  xor               gate primitive, xor exclusive or

  "net data type" means it starts a declaration of name(s) that must be driven
  "variable data" means it starts a declaration of name(s) that hold values

File Structure

  <compiler directives>

  module ...        // zero or more module definitions
    <module contents>
  endmodule

  macromodule ...   // zero or more macromodule definitions
    <macromodule contents>
  endmacromodule

  primitive ...     // zero or more primitive definitions
    <primitive contents>
  endprimitive

  config ...       // optional configuration specification
    <configuration statements>
  endconfig
Module Structure (same for macromodule)

  module module_name(<port_name_list>); // (<port_nem_list>) is optional
    input <some_port_names>;            // any port names that are inputs
    output <some_port_names>;           // any port names that are outputs
    inout <some_port_names>;            // any port names that are both

    <specify block>                     // optional specify block

    <declarations>                      // optional variable declarations and
                                        // optional net declarations

    <function definitions>              // optional function definitions

    <task definitions>                  // optional task definitions

    <parallel statements>               // optional module instantiations
                                        // and parallel statements

    initial                             // zero or more initial blocks
      begin
        <sequential statements>
      end

    always                              // zero or more always blocks
      begin
        <sequential statements>
      end

  endmodule                             // physical end of module

  primitive mux(out, ctrl, in1, in2); // sample primitive definition
    output out;
    input  ctrl, in1, in2;
    table // ctrl in1 in2 : out
              0    1   ?  :  1;
              0    0   ?  :  0;
              1    ?   0  :  0;
              1    ?   1  :  1;
              x    0   0  :  0;
              x    1   1  :  1;
              // other cases output x
    endtable
  endprimitive


Sequential Statements

  if(<condition>)
    begin
      <statements>
    end

  if(<condition1>)
    begin
      <statements>
    end
  else if(<condition2>)
    begin
      <statements>
    end
  //                 any number of optional  "else if" clauses
  else               // optional "else" clause
    begin
      <statements>
    end

  case(<expression>) // or  casex  or  casez  for == accepting x or z
    <expression1> : <statement>
    <expression2> : begin
                      <statements>
                    end
    <expression3>,             // note comma
    <expression4>: <statement> // for both expression==expression3
                               // and expression==expression4
    ...
    default : <statement>      // optional
  endcase

  for(var=initial_expression ; condition; var=update_expression)
  begin
    <statements>
  end

  repeat(<count>)  // block of statements repeated <count> times
  begin
    <statements>
  end

  while(<condition>)  // block of statements repeated while <condition> is true
  begin
    <statements>
  end

  forever  // loop forever
  begin
    <statements>
  end

  begin
    <statements> // executed sequentially
  end

  fork
    <statements> // executed in parallel
  join           // wait until all statements finish

  fork
    begin        // block of statements executing in parallel
      <statements>
    end
    begin        // any number of parallel blocks
      <statements>
    end
  join          // wait until all blocks have finished

  wait(<condition>) #(<optional_delay) <statement>
  wait(<condition>)  // waits for condition to become true (non-zero)

  @(negedge clock) <statement>
  #20;  // delay 20 time units


Parallel Statements

  statements executed between  fork ... join
  assign var = expression; // var is updated when <expression> changes


Gate Primitives

  and    (out, in1, in2, ...);
  nand   (out, in1, in2, ...);
  or     (out, in1, in2, ...);
  nor    (out, in1, in2, ...);
  xor    (out, in1, in2, ...);
  xnor   (out, in1, in2, ...);
  not    (out1, out2, ... , in);
  notif0 (out, in, control);
  notif1 (out, in, control);
  buf    (out1, out2, ... , in);
  bufif0 (out1, in, control);
  bufif1 (out1, in, control);
  pullup (out);
  pulldown (out);

  and #(<timing>) my_name(out_sig, in_sig1, in_sig2); // typical use


System Tasks and Functions

  $display("<format>", exp1, exp2, ...);  // formatted write to display
    format indication %b %B binary
                      %c %C character (low 8 bits)
                      %d %D decimal  %0d for minimum width field
                      %e %E E format floating point %15.7E
                      %f %F F format floating point %9.7F
                      %g %G G general format floating point
                      %h %H hexadecimal
                      %l %L library binding information
                      %m %M hierarchical name, no expression
                      %o %O octal
                      %s %S string, 8 bits per character, 2'h00 does not print
                      %t %T simulation time, expression is  $time
                      %u %U unformatted two value data  0 and 1 
                      %v %V net signal strength
                      %z %Z unformatted four value data  0, 1, x, z
 
    escape sequences, quoted characters in strings \n   newline
                                                   \t   tab
                                                   \\   backslash
                                                   \"   quote
                                                   \ddd octal
                                                   %%   percent
    any other characters between the quotes are displayed
    the expressions are taken in order of the format indication
    ,, in the expression list inserts one space in the output

  $write     // same as $display except no automatic insertion of newline
  $strobe    // same as $display except waits until all events finished
  $monitor   // same as $display except only displays if an expression changes
  $monitoron // only one $monitor may be active at ant time,
  $monitoroff // turn current $monitor off

  $displayb  // same as $display using binary as default format
  $writeb    // same as $write using binary as default format
  $strobeb   // same as $strobe using binary as default format
  $monitorb  // same as $monitor using binary as default format
  $displayo  // same as $display using octal as default format
  $writeo    // same as $write using octal as default format
  $strobeo   // same as $strobe using octal as default format
  $monitoro  // same as $monitor using octal as default format
  $displayh  // same as $display using hexidecimal as default format
  $writeh    // same as $write using hexadecimal as default format
  $strobeh   // same as $strobe using hexadecimal as default format
  $monitorh  // same as $monitor using hexadecimal as default format

  fd = $fopen("<file name>"); // open a file for writing,
                              // fd is an integer file descriptor
  fd = $fopen("<file name>", file_type); // open a file for file_type action:
                                         // open for reading "r", "rb" binary
                                         // open for writing "w", "wb" binary
                                         // open for append  "a", "ab" binary
                                  // open for read/write "r+", "r+b", "rb+"
                                  // open for write/read "w+", "w+b", "wb+"
                                  // open for append update "a+", "a+b", "ab+"
  $fclose(fd);  // close an opened file
  $frewind(fd); // rewind an opened file
  $fflush(fd);  // flush pending output to an open file
  $fseek(
  $ftell(

  $fdisplay(fd, 
  $fwrite(fd,
  $swrite(??
  $fstrobe(fd,
  $fmonitor(fd,
  $fread(fd,
  $fscanf(fd,

  $fdisplayb  // same as $fdisplay using binary as default format
  $fwriteb    // same as $fwrite using binary as default format
  $swriteb    // same as $swrite using binary as default format
  $fstrobeb   // same as $fstrobe using binary as default format
  $fmonitorb  // same as $fmonitor using binary as default format
  $fdisplayo  // same as $fdisplay using octal as default format
  $fwriteo    // same as $fwrite using octal as default format
  $swriteo    // same as $swrite using octal as default format
  $fstrobeo   // same as $fstrobe using octal as default format
  $fmonitoro  // same as $fmonitor using octal as default format
  $fdisplayh  // same as $fdisplay using hexidecimal as default format
  $fwriteh    // same as $fwrite using hexadecimal as default format
  $swriteh    // same as $swrite using hexadecimal as default format
  $fstrobeh   // same as $fstrobe using hexadecimal as default format
  $fmonitorh  // same as $fmonitor using hexadecimal as default format

  $sscanf
  $sdf_annotate


Compiler Directives

  Compiler directives begin with "`" an accent grave, not an apostrophe
  Some of these would be called preprocessor commands in "C"

  `include file_name   // include source code from another file
  `define macro_name macro_code  // substitute macro_code for macro_name
  `define macro_name(par1, par2,...) macro_code  // parameterized macro
  `undef  macro_name             // undefine a macro

  `ifdef  macro_name1 // include source lines1 if macro_name1 is defined
     <source lines1>
  `elsif macro_name2  // any number of elsif clauses, the first defined
     <source lines2>  // macro_name includes the source lines
  `else               // include source lines3 when no prior macro_name defined
     <source lines3>
  `endif              // end the construct
  `ifndef macro_name  // like `ifdef except logic is reversed,
                      // true if macro_name is undefined

  `timescale 1ns/1ns  // units/precision for time  e.g. for %t
  `celldefine         // marks beginning of a cell
  `endcelldefine      // marks end of a cell

  `default_nettype net_type  // sets the default net type for implicit
                             // net declarations, net_type is one of:
       // wire, tri, tri0, tri1, triand, trior, trireg, wand, wor, none

  `resetall           // reset all directives to default state,
                      // undefine all macros
  `line number "filename" level // over rides the compilers information
  `unconnected_drive pull0  // set unconnected inputs to 0
  `unconnected_drive pull1  // set unconnected inputs to 1
  `nounconnected_drive      // terminates either of the above directives
  `default_decay_time a_time // sets all undefined trireg net decay times,
                             // a_time is integer, real or infinite
  `default_trireg_strength val // default trireg net strength 0 to 250
  `delay_mode_distributed    // sets distributed delay mode
  `delay_mode_path           // sets path delay mode
  `delay_mode_unit           // sets unit delay mode
  `delay_mode_zero           // sets zero-delay mode

  Compilers may add additional compiler directives. They may not be
  portable and may not invoke the same actions.

Net Declaration Statements

   These can not hold a value. They must have a driver and
   they have the value given by the driver.
   supply0, supply1, tri, triand, trior, tri0, tri1, wire, wand, wor

   wire (31:0) a_bus;   
   input wire [7:0] a, b, c; // combined declaration


Variable Declaration Statements

   value changes on assignment, retains value until changed
   integer, real, realtime, reg, time

   integer i;
   integer j=7;
   integer stuff[1:10];        // array
   real x = 3.5;
   realtime t1 = 255.5;
   reg a;
   reg clk;
   reg (31:0) word;    // vector[7] = 1;
   reg (4:7)  bits = 4'b1001;
   reg (7:0) byte_mem[0:1023]; // 1024 bytes
   time    soon;
   time    more[5:20];         // array
   integer D3 [1:10][1:10][1:10]; // 3D array
   output reg [31:0] y;      // combined declaration

   There is no type "character" or "string."
   reg [8*14:1] = "hello world"; // allows up to 14 characters

Timing formats

  #10 <statement> // the statement execution takes 10 time units 
                  // (blocking, next statement waits the 10 time units)
  #10 var <= expression; // non blocking statement, var takes 10 time units
                         // to update but next statement proceeds with no delay
  #(12.5 : 15 : 18.2) <statement> // minimum : typical : maximum time units
  #(12.5 : 15 ; 18.2 , 15.2 : 20.1 : 30) <statement>
  //rising times, falling times  each minimum : typical : maximum

  and #5 (out, in1, in2, ...);  // delay from input to output
  and #(5,6) (out, in1, in2, ...); // rising and falling delay
  and #(4:5:6) (out, in1, in2, ...); // min : typical : max delay
  and #(4:5:6 , 5:6:7) (out, in1, in2, ...); // min:typ:max on rise and fall
  buf #(4, 5 , 10) (out, in); // rising, falling, and transport delay
  buf #(4:5:6 , 5:6:7 , 6:7:8) (out, in); // full timing specification


Predefined user logic-value system

   0  a zero or false or low, written  0
   1  a one  or true  or high, written  1
   x  an uninitialized or unknown, written  1'bx
   z  a high impedance, written  1'bz

   There is an extended internal logic-value system